cvdp_nonagentic_no_commercial_copilot_comparator_0001

提交解答
分數： 100
時間限制： 1.0s
記憶體限制： 256M
作者：
m1145505
題目代碼
題目類型
允許的語言
Verilog

Create a fully parameterized SystemVerilog module for a comparator that can operate in two modes: "signed mode" and "magnitude mode." The module should compare two signed integers of parameterized bit width and output signals to indicate whether one input is greater than, less than, or equal to the other. The design should be a purely combinational circuit and include an enabled input that activates the comparison.

Specifications
  1. Module Name: signed_unsigned_comparator
  2. Parameterization:
    • WIDTH: Defines the bit-width of the inputs (default value: 5).
  3. Inputs and Outputs:
Signal Direction Bit Width Active State Description
i_A Input WIDTH N/A WIDTH-bit integer input value, to be compared with i_B.
i_B Input WIDTH N/A WIDTH-bit integer input value, to be compared with i_A.
i_enable Input 1 High Enable signal for comparison. When low, all outputs (o_greater, o_less, o_equal) are inactive.
i_mode Input 1 High Mode selection signal: high for "signed mode," low for "magnitude mode".
o_greater Output 1 High Output signal indicating i_A > i_B. Active when i_enable is high and i_A is greater than i_B.
o_less Output 1 High Output signal indicating i_A < i_B. Active when i_enable is high and i_A is less than i_B.
o_equal Output 1 High Output signal indicating i_A == i_B. Active when i_enable is high and i_A equals i_B.
Behavioral Requirements

  • The module should support two comparison modes:

    • Signed Mode: If i_mode is high, the comparison interprets i_A and i_B as signed integers, where the most significant bit (MSB) represents the sign (1 for negative, 0 for positive).
    • Magnitude Mode: If i_mode is low, the comparison ignores the sign bit and treats both inputs as unsigned magnitudes.

  • When i_enable is high, the module should perform the comparison according to the selected mode:

    • If i_A > i_B, o_greater should be high, and o_less and o_equal should be low.
    • If i_A < i_B, o_less should be high, and o_greater and o_equal should be low.
    • If i_A == i_B, o_equal should be high, and o_greater and o_less should be low.

  • When i_enable is low, all outputs (o_greater, o_less, o_equal) should be set to low, regardless of the comparison mode or inputs.

Constraints and Edge Cases
  • Ensure the module correctly handles edge cases for maximum positive and maximum negative values in signed mode, as well as for the largest and smallest possible magnitudes in magnitude mode.
  • The design should fully handle the i_enable signal, keeping outputs low when disabled.
  • Ensure that parameterization for WIDTH is respected throughout the design, allowing easy modification of input bit-width without further changes to the logic.
Additional Notes
  • Follow purely combinational design requirements—no sequential elements.
  • Ensure the module is synthesizable and uses industry-standard terminology throughout the code and documentation.

評論

目前沒有評論。